module addr_decode (
  input   wire         clk_n,
  input   wire         rst_n,
  input   wire  [6:0]  addr,
  input   wire  [7:0]  data,
  output  wire  [6:0]  d_addra,
  output  wire         d_ena,
  output  reg   [7:0]  leds
);

assign d_addra[6:0] = addr;

assign d_ena        = (addr[6] == 1'b0) ? 1'b1 : 1'b0;

always @(posedge clk_n or negedge rst_n) begin
  if (rst_n == 1'b0) begin
    leds <= 8'b0;
  end else begin
    if (addr[6:0] == 7'b100_0000) begin
      leds <= data[7:0];
    end
  end
end


endmodule
